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a tigersharc and the tigersharc logo are registered trademar ks of analog devices, inc. tigersharc ? embedded processor adsp-ts203s rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.3113 ? 2006 analog devices, inc. all rights reserved. key features 500 mhz, 2.0 ns instruction cycle rate 4m bits of internalon-chipdram memory 25 mm 25 mm (576-ball) thermally enhanced ball grid array package dual-computation blockseach containing an alu, a multi- plier, a shifter, and a register file dual-integer alus, providing data addressing and pointer manipulation single-precision ieee 32-bit an d extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats integrated i/o includes 10-ch annel dma controller, external port, two link ports, sdram controller, programmable flag pins, two timers, and timer expired pin for system integration 1149.1 ieee-compliant jtag te st access port for on-chip emulation on-chip arbitration for glueless multiprocessing key benefits provides high performance static superscalar dsp operations, optimized for large, demanding multiprocessor dsp applications performs exceptionally well on dsp algorithm and i/o benchmarks (see benchmarks in table 1 ) supports low overhead dma transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) dsps eases programming through extr emely flexible instruction set and high-level-language-friendly dsp architecture enables scalable multiproce ssing systems with low commu- nications overhead figure 1. function al block diagram t l0 4 8 4 8 4 8 4 8 4 in out host multi- proc c-bus arb data 32 link ports jtag port external port addr 32 6 soc bus dma jtag sdram ctrl ext dma req j-bus data iab pc btb addr fetch program sequencer computational blocks j-bus addr k-bus data k-bus addr i-bus data i-bus addr s-bus data s-bus addr integer kalu integer jalu 32 32 32-bit 32-bit data address generation x register file 32-bit 32-bit mul alu shift dab 128 128 dab 128 128 memory blocks a d 4m bits internal memory 4 crossbar connect (page cache) a d a d a d soc i/f y register file 32-bit 32-bit mul alu shift l1 in out ctrl 8 ctrl 10 32 128 32 128 32 128 21 128 4 32-bit 32-bit
rev. c | page 2 of 48 | december 2006 adsp-ts203s table of contents general description ................................................. 3 dual compute blocks ............................................ 4 data alignment buffer (dab) .................................. 4 dual integer alu (ialu) ....................................... 4 program sequencer ............................................... 5 interrupt controller ........................................... 5 flexible instruction set ........................................ 5 dsp memory ....................................................... 5 external port (off-chip memory/peripherals interface) ......................................................... 6 host interface ................................................... 7 multiprocessor interface ...................................... 7 sdram controller ............................................ 7 eprom interface .............................................. 7 dma controller ................................................... 7 link ports (lvds) ................................................ 9 timer and general-purpose i/o ............................... 9 reset and booting ................................................. 9 clock domains .................................................... 9 power domains .................................................. 10 filtering reference voltage and clocks .................... 10 development tools ............................................. 10 evaluation kit .................................................... 11 designing an emul ator-compatible dsp board (target) .......................................... 11 additional information ........................................ 11 pin function descriptions ....................................... 12 strap pin function descriptions ................................ 19 adsp-ts203sspecifications .. ................................ 20 operating conditions .......................................... 20 electrical characteristics ....................................... 21 absolute maximum ratings .................................. 22 package information ........................................... 22 esd sensitivity ................................................... 22 timing specifications .......................................... 23 general ac timing .......................................... 23 link port low voltage, di fferential-signal (lvds) electrical characteristics, and timing ................ 29 link portdata out timing ........................... 30 link portdata in timing ............................. 33 output drive currents ......................................... 35 test conditions .................................................. 36 output disable time ......................................... 36 output enable time ......................................... 37 capacitive loading ........................................... 37 environmental conditions .................................... 39 thermal characteristics ..................................... 39 576-ball bga_ed pin configurations ......................... 40 outline dimensions ................................................ 44 surface mount design .......................................... 44 ordering guide ..................................................... 45 revision history 11/06rev. b to rev. c applied corrections and additional information to: figure 7, sclk_vref filtering scheme .................... 10 operating conditions ........................................... 20 added on-chip dram refresh ............................. 26 ordering guide .................................................. 45
adsp-ts203s rev. c | page 3 of 48 | december 2006 general description the adsp-ts203s tigersharc pr ocessor is an ultrahigh per- formance, static superscalar proc essor optimized for large signal processing tasks and communications infrastructure. the dsp combines very wide memory widths with dual computation blockssupporting floating-poi nt (ieee 32-bit and extended precision 40-bit) and fixed-poin t (8-, 16-, 32-, and 64-bit) pro- cessingto set a new standard of performance for digital signal processors. the tigersharc static superscalar architecture lets the dsp execute up to four instru ctions each cycle, performing 24 fixed-point (16-bit) operat ions or six floating-point operations. four independent 128-bit wide internal data buses, each con- necting to the four 1m bit memo ry banks, enable quad-word data, instruction, and i/o acce ss and provide 28g bytes per sec- ond of internal memory bandwidth. operating at 500 mhz, the adsp-ts203s processors core has a 2.0 ns instruction cycle time. using its single-instruction, multiple-data (simd) fea- tures, the adsp-ts203s proces sor can perform four billion, 40-bit macs or one billion , 80-bit macs per second. table 1 shows the dsps performance benchmarks. the adsp-ts203s processor is co de compatible with the other tigersharc processors. the functional block diagram on page 1 shows the adsp-ts203s processors architectural blocks. these blocks include ? dual compute blocks, each consisting of an alu, multi- plier, 64-bit shifter, and 32-word register file and associated data alignment buffers (dabs) ? dual integer alus (ialus), each with its own 31-word register file for data addressing and a status register ? a program sequencer with in struction alignment buffer (iab) and branch target buffer (btb) ? an interrupt controller that supports hardware and soft- ware interrupts, supports l evel- or edge-triggers, and supports prioritized, nested interrupts ? four 128-bit internal data buse s, each connecting to the four 1m-bit memory banks ?on-chip dram (4m-bit) ? an external port that provides the interface to host proces- sors, multiprocessing space (dsps), off-chip memory- mapped peripherals, and ex ternal sram and sdram ? a 10-channel dma controller ? two full-duplex lvds link ports ? two 64-bit interval time rs and timer expired pin ? an 1149.1 ieee-compliant jtag test access port for on- chip emulation figure 2 shows a typical single-proce ssor system with external sram and sdram. figure 4 on page 8 shows a typical multi- processor system. table 1. general-purpose algorithm benchmarks at 500 mhz benchmark speed clock cycles 32-bit algorithm, 1 billion macs/s peak performance 1k point complex fft 1 (radix2) 1 cache preloaded. 18.8 s 9419 64k point complex fft 1 (radix2) 2.8 ms 1397544 fir filter (per real tap) 1 ns 0.5 [8 8][8 8] matrix multiply (complex, floating-point) 2.8 s 1399 16-bit algorithm, 4 billion macs/s peak performance 256 point complex fft 1 (radix 2) 1.9 s 928 i/o dma transfer rate external port 500m bytes/s n/a link ports (each) 500m bytes/s n/a figure 2. adsp-ts203s single-proce ssor system with external sdram boff controlimp10 dmar3C0 hbg hbr dma deice optional data msh flag30 id20 ioen ras cas ldqm sdwe sdcke sda10 irq3C0 sclk sclkrat20 sclk_ ref ref tmr0e bm mssd3C0 buslock sdram memor optional cs ras cas dqm we cke a10 addr data clk por_in tag adspts203s bms clock link deices 2 ma optional boot eprom optional addr memor optional oe data addr data host processor interface optional ack br7C0 cpa ms1C0 data310 data addr cs ack we addr310 d a t a c o n t r o l a d d r e s s brst reference rd wrl dpa ds20 cs lxclkinpn lxacko lxdati30pn lxbcmpi lxbcmpo lxdato30pn lxclkoutpn lxacki iord iowr rst_out rst_in reference
rev. c | page 4 of 48 | december 2006 adsp-ts203s the tigersharc dsp uses a static superscalar tm ? architecture. this architecture is superscala r in that the adsp-ts203s pro- cessors core can execute simultan eously from one to four 32-bit instructions encoded in a very large instruction word (vliw) instruction line using the dsps dual compute blocks. because the dsp does not perform instruction reordering at runtime the programmer selects which oper ations will execute in parallel prior to runtimethe order of instructions is static. with few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a 10-deep processor pipeline. for optimal dsp program execut ion, programmers must follow the dsps set of instruction para llelism rules when encoding an instruction line. in general, the selection of instructions that the dsp can execute in parallel each cycle depends both on the instruction line resources each instruction requires and on the source and destinatio n registers used in the instructions. the programmer has direct control of three core componentsthe ialus, the compute blocks, and the program sequencer. the adsp-ts203s proce ssor, in most cases, has a two-cycle execution pipeline that is fully interlocked, sowhenever a computation result is unavailable for another operation depen- dent on itthe dsp automatica lly inserts one or more stall cycles as needed. efficient pr ogramming with dependency-free instructions can eliminate most computational and memory transfer data dependencies. in addition, the adsp-ts203s processor supports simd opera- tions two wayssimd compute blocks and simd computations. the programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution). dual compute blocks the adsp-ts203s processor ha s compute blocks that can execute computations either inde pendently or together as a sin- gle-instruction, multiple-data (simd) engine. the dsp can issue up to two compute instru ctions per compute block each cycle, instructing the alu, mult iplier, or shifter to perform independent, simultaneous oper ations. each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit simd computations in parallel with the operation in the other block. these computation units support ieee 32-bit single-precision floating-point, extended-precisi on 40-bit floating point, and 8-, 16-, 32-, and 64-bit fi xed-point processing. the compute blocks are referred to as x and y in assembly syn- tax, and each block contains three computational unitsan alu, a multiplier, a 64-bit shifterand a 32-word register file. ? register fileeach compute block has a multiported 32-word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned). ? aluthe alu performs a standard set of arithmetic operations in both fixed- and floating-point formats. it also performs logic and permute operations. ? multiplierthe multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate. ? shifterthe 64-bit shifter performs logical and arithmetic shifts, bit and bit stream manipulation, and field deposit and extraction operations. using these features, the compute blocks can ? provide 8 macs per cycle pe ak and 7.1 macs per cycle sustained 16-bit performance and provide 2 macs per cycle peak and 1.8 macs per cycle sustained 32-bit perfor- mance (based on fir) ? execute six single-precision floating-point or execute 24 fixed-point (16-bit) operat ions per cycle, providing 3g flops or 12.0g/s regular operations performance at 500 mhz ? perform two complex 16-bit macs per cycle data alignment buffer (dab) the dab is a quad-word fifo that enables loading of quad- word data from nonaligned addr esses. normally, load instruc- tions must be aligned to their data size so that quad words are loaded from a quad-aligned ad dress. using the dab signifi- cantly improves the efficiency of some applications, such as fir filters. dual integer alu (ialu) the adsp-ts203s processor has two ialus that provide pow- erful address generation capabilities and perform many general- purpose integer operations. the ia lus are referred to as j and k in assembly syntax and have the following features: ? provide memory addresses for data and update pointers ? support circular buffering and bit-reverse addressing ? perform general-purpose integer operations, increasing programming flexibility ? include a 31-word regist er file for each ialu as address generators, the ialus perform immediate or indi- rect (pre- and post-modify) ad dressing. they perform modulus and bit-reverse operations with no constraints placed on mem- ory addresses for the modulus data buffer placement. each ialu can specify either a single-, dual-, or quad-word access from memory. the ialus have hardware support for circular buffers, bit reverse, and zero-overhead loopin g. circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal proc essing, and they are commonly used in digital filt ers and fourier transforms. each ialu pro- vides registers for four circular buffers, so applications can set ? static superscalar is a trademark of analog devices, inc.
adsp-ts203s rev. c | page 5 of 48 | december 2006 up a total of eight circular bu ffers. the ialus handle address pointer wraparound automatically, reducing overhead, increas- ing performance, and simplify ing implementation. circular buffers can start and end at any memory location. because the ialus computational pipeline is one cycle deep, in most cases integer results are avai lable in the next cycle. hard- ware (register dependency check) causes a stall if a result is unavailable in a given cycle. program sequencer the adsp-ts203s processors pr ogram sequencer supports the following: ? a fully interruptible programm ing model with flexible pro- gramming in assembly and c/c++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles ? a 10-cycle instruction pipelinefour-cycle fetch pipe and six-cycle execution pipecom putation results available two cycles after operands are available ? supply of instruction fetc h memory addresses; the sequencers instruction alignment buffer (iab) caches up to five fetched instruction lines waiting to execute; the pro- gram sequencer extracts an in struction line from the iab and distributes it to the a ppropriate core component for execution ? management of program structures and program flow determined according to ju mp, call, rti, rts instruc- tions, loop structures, condit ions, interrupts, and software exceptions ? branch prediction and a 128-entry branch target buffer (btb) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correct ly predicted branches occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty ? compact code without the requirement to align code in memory; the iab handles alignment interrupt controller the dsp supports nested and nonn ested interrupts. each inter- rupt type has a register in the interrupt vector table. also, each has a bit in both the interrupt latch register and the interrupt mask register. all interrupts are fi xed as either level-sensitive or edge-sensitive, except the irq3C0 hardware interrupts, which are programmable. the dsp distinguishes between hardware interrupts and soft- ware exceptions, handling them differently. when a software exception occurs, the dsp aborts all other instructions in the instruction pipe. when a hardware interrupt occurs, the dsp continues to execute instructions already in the instruction pipe. flexible instruction set the 128-bit instruction line, whic h can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. for example, one instruction line can direct the dsp to conditionally ex ecute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the progra m. some key features of the instruction set include: ? algebraic assembly language syntax ? direct support for all dsp, imaging, and video arithmetic types ? eliminates toggling dsp hard ware modes because modes are supported as options (for example, rounding, satura- tion, and others) within instructions ? branch prediction encoded in instruction; enables zero- overhead loops ? parallelism encoded in instruction line ? conditional execution optional for all instructions ? user-defined partitioning between program and data memory dsp memory the dsps internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in figure 3 . the memory map is divided into four memory areashost space, external memory, multiprocessor space, and internal memoryand each memory space, except host memory, is sub- divided into smaller memory spaces. the adsp-ts203s processor inte rnal memory has 4m bits of on-chip dram memory, divided into four blocks of 1m bits (32k words 32 bits). each blockm0, m2, m4, and m6can store program instructions, data, or both, so applications can configure memory to suit spec ific needs. placing program instructions and data in different memory blocks, however, enables the dsp to access data wh ile performing an instruction fetch. each memory segment contains a 128k bit cache to enable single-cycle accesses to internal dram. the four internal memory blocks connect to the four 128-bit wide internal buses through a cr ossbar connection, enabling the dsp to perform four memory tran sfers in the same cycle. the dsps internal bus architecture provides a tota l memory band- width of 28g bytes per second, enabling the core and i/o to access eight 32-bit data-words a nd four 32-bit instructions each cycle. the dsps flexible memory structure enables ? dsp core and i/o access to di fferent memory blocks in the same cycle ? dsp core access to three memory blocks in parallelone instruction and two data accesses ? programmable partitioning of program and data memory ? program access of all memo ry as 32-, 64-, or 128-bit words16-bit words with the dab
rev. c | page 6 of 48 | december 2006 adsp-ts203s external port (off-chip memory/peripherals interface) the adsp-ts203s processors exte rnal port provides the dsps interface to off-chip memory and peripherals. the 4g word address space is included in th e dsps unified address space. the separate on-chip busesfour 128-bit data buses and four 32-bit address busesare multiplexed at the soc interface and transferred to the external port over the soc bus to create an external system bus transaction. the exte rnal system bus pro- vides a single 32-bit data bus and a single 32-bit address bus. the external port su pports data transfer rates of 500m bytes per second over the external bus. the external bus is configured for 32-bit, little-endian opera- tions. unlike the adsp-ts201, the adsp-ts203s processors external port cannot support 64-bit operations; the external bus width control bits (bits 21-19) must = 0 in the syscon regis- terall other values are illegal for the ad sp-ts203s processor. because the external port is restricted to 32 bits on the adsp- ts203s processor, there are a number of pinout differences between the adsp-ts203s proc essor and the adsp-ts201 processor. the external port supports pi pelined, slow, and sdram proto- cols. addressing of external memory devices and memory- mapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals. the adsp-ts203s processor prov ides programmable memory, pipeline depth, and idle cycl e for synchronous accesses, and external acknowledge controls to support interf acing to pipe- lined or slow devices, host processors, and other memory- mapped peripherals with variable access, hold, and disable time requirements. figure 3. adsp-ts2 03s memory map reserved internal registers (uregs) internal memory block 4 internal memory block 2 internal memory block 0 0x0 3ffffff 0x001e0000 0x001e03ff 0x000c7fff 0x0 00 c000 0 0x 000 87 fff 0x00080000 0x 000 47 fff 0x00040000 0x 000 07 fff 0 x0 00 000 00 internal space processor id 7 processor id 6 processor id 5 processor id 4 processor id 3 processor id 2 processor id 1 processor id 0 broadcast host ( ms h ) bank 1( ms1 ) bank 0( ms0 ) mssd bank 0 ( ms sd 0 ) internal memory 0x50000000 0 x4 000 00 00 0x38000000 0x30000000 0x2c000000 0x28000000 0x24000000 0x20000000 0x1c000000 0x18000000 0x14000000 0x10000000 0x0c000000 0x03ffffff 0x00000000 global space 0xffffffff m u l t i p r o c e s s o r m e m o r y s p a c e e x t e r n a l m e m o r y s p a c e each is a copy of internal space reserved internal memory block 6 reserved reserved soc registers (uregs) 0x 00 1f00 00 0 x00 1f03 ff mssd bank 1 ( ms sd 1 ) mssd bank 2 ( ms sd 2 ) mssd bank 3 ( ms sd 3 ) 0x60000000 0x70000000 0x80000000 re ser v ed re ser v ed re ser v ed re ser v ed 0x54000000 0 x4 400 00 00 0x64000000 0x74000000 reserved reserved reserved
adsp-ts203s rev. c | page 7 of 48 | december 2006 host interface the adsp-ts203s processor provid es an easy and configurable interface between its external bu s and host processors through the external port. to accommodat e a variety of host processors, the host interface supports pipe lined or slow protocols for adsp-ts203s processor access of th e host as slave or pipelined for host access of the adsp-ts2 03s processor as slave. each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles. the host interface supports burst tr ansactions initiated by a host processor. after the host issues the starting address of the burst and asserts the brst signal, the dsp increments the address internally while the host continues to assert brst . the host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the dsp. the boff signal provides the de adlock recovery mecha- nism. when the host asserts boff , the dsp backs off the current transactio n and asserts hbg and relinquishes the external bus. the host can directly read or write the internal memory of the adsp-ts203s processor, and it can access most of the dsp reg- isters, including dma control (tcb) registers. vector interrupts support efficient ex ecution of host commands. multiprocessor interface the adsp-ts203s proce ssor offers powerful features tailored to multiprocessing dsp systems through the external port and link ports. this multiprocessing capability provides the highest bandwidth for interprocessor communication, including ? up to eight dsps on a common bus ? on-chip arbitration fo r glueless multiprocessing ? link ports for point-to-point communication the external port and link po rts provide integrated, glueless multiprocessing support. the external port supports a unified address space (see figure 3 ) that enables direct interpro cessor accesses of each adsp- ts203s processors internal memo ry and register s. the dsps on-chip distributed bus arbitratio n logic provides simple, glue- less connection for systems containing up to eight adsp-ts203s processors and a ho st processor. bus arbitration has a rotating priority. bus lo ck supports indivisible read- modify-write sequences for sema phores. a bus fairness feature prevents one dsp from holdin g the external bus too long. the dsps two link ports provide a second path for interproces- sor communications with throug hput of 1g byte per second. the cluster bus provides 500m by tes per second throughput with a total of 1.5g bytes per second interprocessor bandwidth. sdram controller the sdram controller controls the adsp-ts203s processors transfers of data to and from external synchronous dram (sdram) at a throughput of 32 bits per sclk cycle using the external port and sdram control pins. the sdram interface provides a glueless interface with stan- dard sdrams16m bits, 64m bi ts, 128m bits, 256m bits and 512m bits. the dsp supports direct ly a maximum of four banks of 64m words 32 bits of sdram. the sdram interface is mapped in external memory in each dsps unified memory map. eprom interface the adsp-ts203s processor can be configured to boot from an external 8-bit eprom at reset through the external port. an automatic process (which follows reset) loads a program from the eprom into internal memory . this process uses 16 wait cycles for each read access. during booting, the bms pin func- tions as the eprom chip sele ct signal. the eprom boot procedure uses dma channel 0, which packs the bytes into 32-bit instructions. applicatio ns can also access the eprom (write flash memories) during normal operation through dma. the eprom or flash memory interface is not mapped in the dsps unified memory map. it is a byte address space limited to a maximum of 16m bytes (24 address bits). the eprom or flash memory interface can be used after boot via a dma. dma controller the adsp-ts203s processors on -chip dma controller, with 10 dma channels, provid es zero-overhead data transfers with- out processor intervention. the dma controller operates independently and invisibly to the dsps core, enabling dma operations to occur while the ds ps core contin ues to execute program instructions. the dma controller performs dm a transfers between internal memory, external memory, and memory-mapped peripherals; the internal memory of other dsps on a common bus, a host processor, or link port i/o; be tween external memory and exter- nal peripherals or link port i/ o; and between an external bus master and internal memory or link port i/o. the dma con- troller performs the fo llowing dma operations: ? external port block transfers. four dedicated bidirectional dma channels transfer blocks of data between the dsps internal memory and any external memory or memory- mapped peripheral on the external bus. these transfers support master mode and handshake mode protocols. ? link port transfers. four dedicated dma channels (two transmit and two receive) tr ansfer quad-word data only between link ports and between a link port and internal or external memory. these tran sfers only use handshake mode protocol. dma priority rotates between the two receive channels. ? autodma transfers. two dedicated unidirectional dma channels transfer data received from an external bus master to internal memory or to link port i/o. these transfers only use slave mode protocol, and an external bus master must initiate the transfer. the dma controller provides these additional features: ? flyby transfers. flyby operations only occur through the external port (dma channel 0) and do not involve the dsps core. the dma controller acts as a conduit to
rev. c | page 8 of 48 | december 2006 adsp-ts203s transfer data from an extern al i/o device to external sdram memory. during a transaction, the dsp relin- quishes the external data bus; outputs addresses and memory selects (mssd3C0 ); outputs the iord , iowr , ioen , and rd /wr strobes; and responds to ack. ? dma chaining. dma chaining operations enable applica- tions to automatically link on e dma transfer sequence to another for continuous tran smission. the sequences can occur over different dma channels and have different transmission attributes. ? two-dimensional transfer s. the dma controller can access and transfer two-dimensional memory arrays on any dma transmit or receive ch annel. these transfers are implemented with index, coun t, and modify registers for both the x and y dimensions. figure 4. adsp-ts203s shared memory multiprocessing system clks/refs addr31?0 data31?0 br1 br7C2,0 addr31?0 data31?0 br0 br7C1 bms control adsp-ts203s #0 control adsp-ts203s #1 adsp-ts203s #7 adsp-ts203s #6 adsp-ts203s #5 adsp-ts203s #4 adsp-ts203s #3 adsp-ts203s #2 reset rst_in id2?0 clks/refs sclk_v ref v ref sclk sclkrat2?0 000 clock reference addr data host processor interface (optional) ack global memory and peripherals (optional) oe addr data cs addr data boot eprom (optional) rd ms1C0 ack id2?0 001 hbg hbr boff brst cs we wrl c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a sdram memory (optional) mssd3C0 iord ioen ras cas ldqm sdwe sdcke sda10 cs ras cas dqm we cke a10 addr data clk msh dmar3C0 dpa cpa link devices (2 max) (optional) lxclkinp/n lxacko lxdati3?0p/n lxbcmpi lxbcmpo lxdato3?0p/n lxclkoutp/n lxacki tmr0e bm controlimp1?0 link irq3C0 flag3?0 link rst_in buslock clock ds2?0 iowr jtag por_in rst_out reference link devices
adsp-ts203s rev. c | page 9 of 48 | december 2006 link ports (lvds) the dsps two full-duplex link ports each prov ide additional four-bit receive and four-bit transmit i/o capability, using low- voltage, differential-signal (lvd s) technology. with the ability to operate at a double data ratel atching data on both the rising and falling edges of the clock running at 250 mhz, each link port can support up to 250m bytes per second per direction, for a combined maximum throughput of 1g byte per second. the link ports provide an opti onal communications channel that is useful in multiprocesso r systems for implementing point- to-point interprocessor communic ations. applications can also use the link ports for booting. each link port has its own triple-buffered quad-word input and double-buffered quad-w ord output registers. the dsps core can write directly to a link ports transmit register and read from a receive register, or the dma controller can perform dma transfers through four (two tran smit and two receive) dedicated link port dma channels. each link port direct ion has three signals that control its opera- tion. for the transmitter, lxclkout is the output transmit clock, lxacki is the handshake input to control the data flow, and the lxbcmpo output indicates that the block transfer is complete. for the receiver, lxclkin is the input receive clock, lxacko is the handshake output to control the data flow, and the lxbcmpi input indicates that the block transfer is com- plete. the lxdato3C0 pins are the data output bus for the transmitter, and the lxdati3C0 pins are the input data bus for the receiver. applications can program separa te error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data pack ets, and the speed at which bytes are transmitted. timer and general-purpose i/o the adsp-ts203s processor ha s a timer pin (tmr0e) that generates output when a programmed timer counter has expired, and four programmable general-purpose i/o pins (flag3C0) that can function as either single-bit input or out- put. as outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching. reset and booting the adsp-ts203s processor ha s three levels of reset: ? power-up reset C after power-up of the system (sclk, all static inputs, and strap pi ns are stable), the rst_in pin must be asserted (low). ? normal reset C for any chip reset following the power-up reset, the rst_in pin must be asserted (low). ? dsp-core reset C when setting the swrst bit in emuctl, the dsp core is reset, but not the external port or i/o. for normal operations, tie the rst_out pin to the por_in pin. after reset, the adsp-ts203s pr ocessor has four boot options for beginnin g operation: ? boot from eprom. ? boot by an external master (host or another adsp-ts203s processor). ?boot by link port. ? no bootstart running from memory address selected with one of the irq3C0 interrupt signals. see table 2 . using the no boot option, th e adsp-ts203s processor must start running from memory when one of the interrupts is asserted. the adsp-ts203s processor core al ways exits from reset in the idle state and waits for an interrupt. some of the interrupts in the interrupt vector table are in itialized and enabled after reset. for more information on boot options, see the ee-200: adsp-ts20x tigersharc processor boot loader kernels oper- ation on the analog devices website ( www.analog.com ) clock domains the dsp uses calculated ratios of the sclk clock to operate, as shown in figure 5 . the instruction execution rate is equal to cclk. a pll from sclk generates cclk which is phase- locked. the sclkratx pins define the clock multiplication of sclk to cclk (see table 4 on page 12 ). the link port clock is generated from cclk via a softwa re programmable divisor, and the soc bus operates at 1/2 ccl k. memory transfers to exter- nal and link port buffers operate at the socclk rate. sclk also provides clock input for the external bus interface and defines the ac specification reference for the external bus signals. the external bus interface runs at the sclk frequency. the maxi- mum sclk frequency is one qu arter the internal dsp clock (cclk) frequency. table 2. no boot, run from memory addresses interrupt address irq0 0x3000 0000 (external memory) irq1 0x3800 0000 (external memory) irq2 0x8000 0000 (external memory) irq3 0x0000 0000 (internal memory) figure 5. clock domains sclkratx sclk spd bits, lctlx register pll /2 /cr cclk (instruction rate) socclk (peripheral bus rate) lxclkout (link output rate) eternal interface
rev. c | page 10 of 48 | december 2006 adsp-ts203s power domains the adsp-ts203s processor ha s separate power supply con- nections for internal logic (v dd ), analog circuits (v dd_a ), i/o buffer (v dd_io ), and internal dram (v dd_dram ) power supply. note that the analog (v dd_a ) supply powers the clock generator plls. to produce a stable clock, systems must provide a clean power supply to power input v dd_a . designs must pay critical attention to bypassing the v dd_a supply. filtering reference voltage and clocks figure 6 and figure 7 show possible circuits for filtering v ref , and sclk_v ref . these circuits provide the reference voltages for the switching voltage refere nce and system clock reference. development tools the adsp-ts203s processor is su pported with a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and visualdsp++ ? ? devel- opment environment. the same emulator hardware that supports other tigersharc processors also fully emulates the adsp-ts203s processor. the visualdsp++ project manage ment environment lets pro- grammers develop and debug an application. this environment includes an easy to use assemble r (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instru ction-level simulator, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathematical functions. a key point for theses tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the dsp has archi- tectural features that improv e the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important features. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representation of user data en ables the programmer to quickly determine the performance of an algorithm. as algorithms grow in complexity, this capability can have increasing significance on the designers development schedule, increasing productiv- ity. statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. this feature, unique to visu aldsp++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the develope r can identify bottlenecks in software quickly and efficiently. by using the profiler, the pro- grammer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ ide lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and ma nage all of the tigersharc processor development tools, in cluding the color syntax high- lighting in the visualdsp++ ed itor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, figure 6. v ref filtering scheme figure 7. sclk_v ref filtering scheme ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc. v dd_io v ss v ref r1 r2 c1 c2 r1: 2k series resistor (1%) r2: 2.55k series resistor (1%) c1: 1 f capacitor (smd) c2: 1nf capacitor (hf smd) placed close to dsp?s pins clock driver voltage or v dd_io v ss sclk_v ref r1 r2 c1 c2 r1: 2k series resistor (1%) r2: 2.55k series resistor (1%) c1: 1 f capacitor (smd) c2: 1nf capacitor (hf smd) placed close to dsp?s pins * if clock driver voltage > v dd_io *
adsp-ts203s rev. c | page 11 of 48 | december 2006 eliminating the need to start from the very beginning when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gen- eration of various vdk-based objects, and visualizing the system state, when debugging an application that uses the vdk. vcse is analog devices techno logy for creating, using, and reusing software components (independent modules of sub- stantial functionality) to quickly and reliably assemble software applications. it is also used for downloading components from the web, dropping them into the application, and publish com- ponent archives from within visualdsp++. vcse supports component implementation in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system, view memory use in a color-coded graphical form, easily move code and data to differ- ent areas of the dsp or external memory with a drag of the mouse, and examine runtime stack and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the developer to move between the graphical and textual environments. analog devices dsp emulators use the ieee 1149.1 jtag test access port of the adsp-ts203s processor to monitor and con- trol the target board processor during emulation. the emulator provides full speed emulation, a llowing inspection and modifi- cation of memory, registers, an d processor stacks . nonintrusive in-circuit emulation is assured by the use of the processors jtag interfacethe emulator do es not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the tigersharc processor family. hardware tools include tigers harc processor pc plug-in cards. third party software tool s include dsp libraries, real- time operating systems, an d block diagram design tools. evaluation kit analog devices offers a range of ez-kit lite ? ? evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board alon g with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample applicat ion programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-kit lite board connects the board to the usb port of the users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot code, enab ling the board to run as a standalone unit, without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom-defined system. connecting one of analog devices jtag emulators to the ez-kit lite bo ard enables high speed, nonin- trusive emulation. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to in order test and debug hardware and software systems. analog de vices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, obse rve variables, observe memory, and examine re gisters. the dsp must be halted to send data and command s, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no im pact on system timing. to use these emulators, the target board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use the string ee-68 in site se arch. this document is updated regularly to keep pace with impr ovements to emulator support. additional information this data sheet provides a general overview of the adsp-ts203s processors architec ture and functionality. for detailed information on the adsp-ts203s processors core architecture and instruction set, see the adsp-ts201 tiger- sharc processor hardware reference and the adsp-ts201 tigersharc processor programming reference . for detailed information on the development to ols for this processor, see the visualdsp++ users guide for tigersharc processors . ? ez-kit lite is a registered trademark of analog devices, inc.
rev. c | page 12 of 48 | december 2006 adsp-ts203s pin function descriptions while most of the adsp-ts203s processors input pins are nor- mally synchronoustied to a specific clocka few are asynchronous. for these asynchronous signals, an on-chip syn- chronization circuit prevents metastability problems. use the ac specification for asynchronous si gnals when the system design requires predictable, cycle-by-c ycle behavior for these signals. the output pins can be three-stated during normal operation. the dsp three-states all output du ring reset, allowing these pins to get to their internal pull-up or pull-down state. some pins have an internal pull-up or pull- down resistor (30% tolerance) that maintains a known value during transitions between differ- ent drivers. table 3. pin definitionsclocks and reset signal type term description sclkrat2C0 i (pd) na core clock ratio. the dsps core clock (cclk) rate = n sclk, where n is user-program- mable using the sclkratx pins to the values shown in table 4 . these pins may change only during reset; connect these pins to v dd_io or v ss . all reset specifications in table 25 , table 26 , and table 27 must be satisfied. the core clock rate (cclk) is the instruction cycle rate. sclk i na system clock input. the dsps system input clock for cluster bus. the core clock rate is user-programmable using the sclkratx pins. for more information, see clock domains on page 9. rst_in i/a na reset. sets the dsp to a known state and causes program to be in idle state. rst_in must be asserted a specified time according to the type of reset operation. for details, see reset and booting on page 9 , table 27 on page 26 , and figure 14 on page 26 . rst_out o na reset output. indicates that the ds p reset is complete. connect to por_in . por_in i/a na power-on reset for internal dram. connect to rst_out . i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss table 4. sclk ratio sclkrat2C0 ratio 000 (default) 4 001 5 010 6 011 7 100 8 101 10 110 12 111 reserved
adsp-ts203s rev. c | page 13 of 48 | december 2006 table 5. pin definitionsexternal port bus controls signal type term description addr31C0 i/o/t (pu_ad) nc address bus. the dsp issues addresses for accessing memory and peripherals on these pins. in a multiprocessor system, the bus master drives addresses for accessing internal memory or i/o processor register s of other adsp-ts203s processors. the dsp inputs addresses when a host or another dsp accesses its internal memory or i/o processor registers. data31C0 i/o/t (pu_ad) nc external data bus. the dsp drives and receives data and instructions on these pins. pull-up or pull-down resistors on unused data pins are unnecessary. rd i/o/t (pu_0) epu 1 memory read. rd is asserted whenever the dsp reads from any slave in the system, excluding sdram. when the dsp is a slave, rd is an input and indicates read trans- actions that access its internal memory or universal registers. in a multiprocessor system, the bus master drives rd . rd changes concurrently with addr pins. wrl i/o/t (pu_0) epu 1 write low. wrl is asserted when the adsp-ts203s processor writes to the external bus (host, memory, or dsp). an external master (host or dsp) asserts wrl for writing to a dsps internal memory. in a multipro cessor system, the bus master drives wrl . wrl changes concurrently with addr pins. when the dsp is a slave, wrl is an input and indicates write transactions that access it s internal memory or universal registers. ack i/o/t/od (pu_od_0) epu 1 acknowledge. external slave devices can deassert ack to add wait states to external memory accesses. ack is used by i/o devices, memory controllers, and other periph- erals on the data phase. the dsp can deassert ack to add wait states to read and write accesses of its internal memory. the pull-up is 50 on low-to-high transactions and is 500 on all other transactions. bms o/t (pu_0) na boot memory select. bms is the chip select for boot eprom or flash memory. during reset, the dsp uses bms as a strap pin (eboot) for eprom boot mode. in a multipro- cessor system, the dsp bus master drives bms . for details, see reset and booting on page 9 and the eboot signal description in table 16 on page 19 . ms1C0 o/t (pu_0) nc memory select. ms0 or ms1 is asserted whenever the dsp accesses memory banks 0 or 1, respectively. ms1C0 are decoded memory address pins that change concurrently with addr pins. when addr31:27 = 0b00110, ms0 is asserted. when addr31:27 = 0b00111, ms1 is asserted. in multiprocessor syst ems, the master dsp drives ms1C0 . msh o/t (pu_0) nc memory select host. msh is asserted whenever the dsp accesses the host address space (addr31 = 0b1). msh is a decoded memory address pin that changes concur- rently with addr pins. in a multiprocesso r system, the bus master dsp drives msh . brst i/o/t (pu_0) epu 1 burst. the current bus master (dsp or host) asse rts this pin to indicate that it is reading or writing data associated with consecutive addresses. a slave device can ignore addresses after the first one and increment an internal address counter after each transfer. for host-to-dsp burst accesses, the dsp increments the address automati- cally while brst is asserted. tm4 i/o/t epu test mode 4. must be pulled up to v dd_io with a 5 k resistor. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss 1 this external pull-up may be omitted fo r the id = 000 tigersharc processor.
rev. c | page 14 of 48 | december 2006 adsp-ts203s table 6. pin definitionsexternal port arbitration signal type term description br7C0 i/o v dd_io 1 multiprocessing bus request pins. used by the dsps in a multiprocessor system to arbitrate for bus mastership. each dsp drives its own brx line (corresponding to the value of its id2C0 inputs) and monitors all others. in systems with fewer than eight dsps, set the unused brx pins high (v dd_io ). id2C0 i (pd) na multiprocessor id. indicates the dsp s id, from which the dsp determines its order in a multiprocessor system. these pins also indicate to the dsp which bus request (br0 Cbr7 ) to assert when requesting the bus: 000 = br0 , 001 = br1 , 010 = br2 , 011 = br3 , 100 = br4 , 101 = br5 , 110 = br6 , or 111 = br7 . id2C0 must have a constant value during system operation and can change during reset only. bm o na bus master. the current bus master dsp asserts bm . for debugging only. at reset this is a strap pin. for more information, see table 16 on page 19 . boff i epu back off. a deadlock situation can occur when the host and a dsp try to read from each others bus at the same time. when deadlock occurs, the host can assert boff to force the dsp to relinquish the bus befo re completing its outstanding transaction. buslock o/t (pu_0) na bus lock indication. provides an indication that the current bus master has locked the bus. at reset, this is a strap pin. for more information, see table 16 on page 19 . hbr i epu host bus request. a host must assert hbr to request control of the dsps external bus. when hbr is asserted in a multiprocessing sy stem, the bus master relinquishes the bus and asserts hbg once the outstanding transaction is finished. hbg i/o/t (pu_0) epu 2 host bus grant. acknowledges hbr and indicates that the host can take control of the external bus. when relinquishing th e bus, the master dsp three-states the addr31C0, data31C0, msh , mssd3C0 , ms1C0 , rd , wrl , bms , brst , iord , iowr , ioen , ras , cas , sdwe , sda10, sdcke, ldqm, and tm4 pins, and the dsp puts the sdram in self-refresh mode. the dsp asserts hbg until the host deasserts hbr . in multiprocessor systems, the current bus master dsp drives hbg , and all slave dsps monitor it. cpa i/o/od (pu_od_0) epu 2 core priority access. asserted while the dsps core accesses external memory. this pin enables a slave dsp to interrupt a master dsps background dma transfers and gain control of the external bus for core-initiated transactions. cpa is an open-drain output, connected to all dsps in the system. if not required in the system, leave cpa unconnected (external pull-ups will be required for dsp id = 1 through id = 7). dpa i/o/od (pu_od_0) epu 2 dma priority access. asserted while a high priority dsp dma channel accesses external memory. this pin enables a high priority dma channel on a slave dsp to interrupt transfers of a normal priority dm a channel on a master dsp and gain control of the external bus for dma-initiated transactions. dpa is an open-drain output, connected to all dsps in the system. if not required in the system, leave dpa uncon- nected (external pull-ups will be required for dsp id = 1 through id = 7). i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss 1 the brx pin matching the id2C0 input se lection for the processor should be left nc if unused. for exampl e, the processor with id = 000 has br0 = nc and br7C1 = v dd_io . 2 this external pull-up resistor may be omit ted for the id = 000 tigersharc processor.
adsp-ts203s rev. c | page 15 of 48 | december 2006 table 7. pin definitionsexternal port dma/flyby signal type term description dmar3C0 i/a epu dma request pins. enable external i/o devices to request dma services from the dsp. in response to dmarx , the dsp performs dma transfers according to the dma channels initialization. the dsp ignores dma requests from uninitialized channels. iowr o/t (pu_0) nc i/o write. when a dsp dma channel initiates a flyby mode read transaction, the dsp asserts the iowr signal during the data cycles. this assertion makes the i/o device sample the data instead of the tigersharc. iord o/t (pu_0) nc i/o read. when a dsp dma channel initiates a flyby mode write transaction, the dsp asserts the iord signal during the data cycle. this assertion with the ioen makes the i/o device drive the data instead of the tigersharc. ioen o/t (pu_0) nc i/o device output enable. enables the output buffers of an external i/o device for fly- by transactions between the device and external memory. active on flyby transactions. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss table 8. pin definitionsexternal port sdram controller signal type term description mssd3C0 i/o/t (pu_0) nc memory select sdram. mssd0 , mssd1 , mssd2 , or mssd3 is asserted whenever the dsp accesses sdram memory space. mssd3C0 are decoded memory address pins that are asserted whenever the dsp issues an sdram command cycle (access to addr31:30 = 0b01except reserved spaces shown in figure 3 on page 6 ). in a multi- processor system, the master dsp drives mssd3C0 . ras i/o/t (pu_0) nc row address select. when sampled low, ras indicates that a row address is valid in a read or write of sdram. in other sdram accesses, it defines the type of operation to execute according to sdram specification. cas i/o/t (pu_0) nc column address select. when sampled low, cas indicates that a column address is valid in a read or write of sdram. in ot her sdram accesses, it defines the type of operation to execute according to the sdram specification. ldqm o/t (pu_0) nc low word sdram data mask. when sampled high, three-states the sdram dq buffers. ldqm is valid on sdram transactions when cas is asserted, and inactive on read transactions. sda10 o/t (pu_0) nc sdram address bit 10. separate a10 sign als enable sdram refresh operation while the dsp executes non-sdram transactions. sdcke i/o/t (pu_m/ pd_m) nc sdram clock enable. activates the sdram clock for sdram self-r efresh or suspend modes. a slave dsp in a multiprocessor sy stem does not have the pull-up or pull- down. a master dsp (or id = 0 in a single processor system) has a pull-up before granting the bus to the host, except when the sdram is put in self refresh mode. in self refresh mode, the master has a pull-down before granting the bus to the host. sdwe i/o/t (pu_0) nc sdram write enable. when sampled low while cas is active, sdwe indicates an sdram write access. when sampled high while cas is active, sdwe indicates an sdram read access. in other sdram accesses, sdwe defines the type of operation to execute according to sdram specification. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss
rev. c | page 16 of 48 | december 2006 adsp-ts203s table 9. pin definitionsjtag port signal type term description emu o/od nc 1 emulation. connected to the dsps jtag emulator target board connector only. tck i epd or epu 1 test clock (jtag). provides an asynchronous clock for jtag scan. tdi i (pu_ad) nc 1 test data input (jtag). a serial data input of the scan path. tdo o/t nc 1 test data output (jtag). a serial data output of the scan path. tms i (pu_ad) nc 1 test mode select (jtag). used to control the test state machine. trst i/a (pu_ad) na test reset (jtag). resets the test state machine. trst must be asserted or pulsed low after power-up for proper device operation. for more information, see reset and booting on page 9 . i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss 1 see the reference on page 11 to the jtag emulation te chnical reference ee-68. table 10. pin definitionsflags, interrupts, and timer signal type term description flag3C0 i/o/a (pu) nc flag pins. bidirectional input/output pins can be used as program conditions. each pin can be configured individually for input or for output. flag3C0 are inputs after power-up and reset. irq3C0 i/a (pu) nc interrupt request. when asserted, the dsp generates an interrupt . each of the irq3C0 pins can be independently set for edge-triggered or level-sensitive operation. after reset, these pins are disabled unless the irq3C0 strap option and interrupt vectors are initialized for booting. tmr0e o na timer 0 expires. this outp ut pulses whenever timer 0 expires. at reset, this is a strap pin. for more information, see table 16 on page 19 . i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss
adsp-ts203s rev. c | page 17 of 48 | december 2006 table 11. pin definitionslink ports signal type term description lxdato3C0p o nc link ports 1C0 data 1C0 transmit lvds p lxdato3C0n o nc link ports 1C0 data 1C0 transmit lvds n lxclkoutp o nc link ports 1C0 transmit clock lvds p lxclkoutn o nc link ports 1C0 transmit clock lvds n lxacki i (pd) nc link ports 1C0 receive acknowledge. using this signal, the receiver indicates to the transmitter that it may continue the transmission. lxbcmpo o (pu) nc link ports 1C0 block completion. when the transmission is executed using dma, this signal indicates to the receiver that the transmitted block is completed. the pull-up resistor is present on l0bcmpo only. at reset, the l1bcmpo pin is a strap pin. for more information, see table 16 on page 19 . lxdati3C0p i v dd_io link ports 1C0 data 3C0 receive lvds p lxdati3C0n i v dd_io link ports 1C0 data 3C0 receive lvds n lxclkinp i/a v dd_io link ports 1C0 receive clock lvds p lxclkinn i/a v dd_io link ports 1C0 receive clock lvds n lxacko o nc link ports 1C0 transmit acknowledge. using this signal, the receiver indicates to the transmitter that it may continue the transmission. lxbcmpi i (pd_l) v ss link ports 1C0 block completion. when the reception is executed using dma, this signal indicates to the receiver that the transmitted block is completed. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k ; pd_l = internal pull-down 50 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss table 12. pin definitionsimpedance control, drive strength control, and regulator enable signal type term description controlimp0 controlimp1 i (pd) i (pu) na na impedance control. as shown in table 13 , the controlimp1C0 pins select between normal driver mode and a/d driver mode. when using normal mode (recommended), the output drive strength is set relative to maximum drive strength according to table 14 . when using a/d mode, the resistance control operates in the analog mode, where drive strength is continuously contro lled to match a specific line impedance as shown in table 14 . ds2, 0 ds1 i (pu) i (pd) na digital drive strength selection. selected as shown in table 14 . for drive strength calcu- lation, see output drive currents on page 35 . the drive strength for some pins is preset, not controlled by the ds2C0 pins. the pins that are always at drive strength 7 (100%) include: cpa , dpa , tdo, emu , and rst_out . the drive strength for the ack pin is always 2 drive strength 7 (100%). enedreg i (pu) v ss connect the enedreg pin to v ss . connect the v dd_dram pins to a properly decoupled dram power supply. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss
rev. c | page 18 of 48 | december 2006 adsp-ts203s table 13. impedance control selection controlimp1-0 driver mode 00 (recommended) normal 01 reserved 10 (default) a/d mode 11 reserved table 14. drive strength/output impedance selection ds2C0 pins drive strength 1 output impedance 2 000 strength 0 (11.1%) 26 001 strength 1 (23.8%) 32 010 strength 2 (36.5%) 40 011 strength 3 (49.2%) 50 100 strength 4 (61.9%) 62 101 (default) strength 5 (74.6%) 70 110 strength 6 (87.3%) 96 111 strength 7 (100%) 120 1 controlimp1 = 0, a/d mode disabled. 2 controlimp1 = 1, a/d mode enabled. table 15. pin definitionspower, ground, and reference signal type term description v dd pnav dd pins for internal logic. v dd_a pnav dd pins for analog circuits. pay critical attention to bypassing this supply. v dd_io pnav dd pins for i/o buffers. v dd_dram pnav dd pins for internal dram. v ref i na reference voltage defines the trip point for all input buffers, except sclk, rst_in , por_in , irq3C0 , flag3C0, dmar3C0 , id2C0, controlimp1C0, lxdato3C0p/n, lxclkoutp/n, lxdati3C0p/n, lxclki np/n, tck, tdi, tms, and trst . v ref can be connected to a power supply or set by a voltage divider circuit as shown in figure 6 . for more information, see filtering reference voltage and clocks on page 10. sclk_v ref i na system clock reference. connect this pin to a reference voltage as shown in figure 7 . for more information, see filtering reference voltage and clocks on page 10. v ss gnaground pins. nc nc no connect. do not connect these pins to anything (not to any supply, signal, or each other). these pins are reserved and must be left unconnected. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to v ss ; epu = external pull-up approx- imately 5 k to v dd_io , nc = not connected; na = not applicable (always used); v dd_io = connect directly to v dd_io ; v ss = connect directly to v ss
adsp-ts203s rev. c | page 19 of 48 | december 2006 strap pin function descriptions some pins have alternate functi ons at reset. strap options set dsp operating modes. during re set, the dsp samples the strap option pins. strap pins have an internal pull-up or pull-down for the default value. if a strap pin is not connected to an over- driving external pull-up, pull-d own, or logic load, the dsp samples the default value during reset. if strap pins are con- nected to logic inputs, a stronger external pull-up or pull-down may be required to ensure defa ult value depending on leakage and/or low level input current of the logic load. to set a mode other than the default mode, connect the strap pin to a suffi- ciently stronger external pull-up or pull-down. table 16 lists and describes each of the dsps strap pins. when default configuration is us ed, no external resistor is needed on the strap pins. to apply other configurations, a 500 resistor connected to v dd_io is required. if providing external pull-downs, do not strap these pins directly to v ss ; the strap pins require 500 resistor straps. all strap pins are sampled on the rising edge of rst_in (deas- sertion edge). each pin latches the strapped pin state (state of the strap pin at the rising edge of rst_in ). shortly after deas- sertion of rst_in , these pins are reconfigured to their normal functionality. these strap pins have an intern al pull-down resistor, pull-up resistor, or no-resistor (three-state) on each pin. the resistor type, which is connected to th e i/o pad, depends on whether rst_in is active (low) or if rst_in is deasserted (high). table 17 shows the resistors that are enabled during active reset and during normal operation. table 16. pin definitionsi/o strap pins signal type (at reset) on pin description eboot i (pd_0) bms eprom boot. 0 = boot from eprom immediately after reset (default) 1 = idle after reset and wait for an external device to boot dsp through the external port or a link port irqen i (pd) bm interrupt enable. 0 = disable and set irq3C0 interrupts to edge-sensitive after reset (default) 1 = enable and set irq3C0 interrupts to level-sensitive immediately after reset link_dwidth i (pd) tmr0e link port input default data width. 0 = 1-bit (default) 1 = 4-bit sys_reg_we i (pd_0) buslock syscon and sdrcon write enable. 0 = one-time writable after reset (default) 1 = always writable tm1 i (pu) l1bcmpo test mode 1. do not overdrive default value during reset. tm2 i (pu) tm2 test mode 2. do not overdrive default value during reset. tm3 i (pu) tm3 test mode 3. do not overdrive default value during reset. i = input; a = asynchronous; o = output; od = open-drain output; t = three-state; p = power supply; g = ground; pd = internal pull-down 5k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0; pu_od_0 = internal pull-up 500 on dsp id = 0; pd_m = internal pull-down 5 k on dsp bus master; pu_m = internal pull-up 5 k on dsp bus master; pu_ad = internal pull-up 40 k . for more pull-down and pull-up information, see electrical characteristics on page 21 . table 17. strap pin internal resistorsactive reset (rst_in = 0) vs. normal operation (rst_in = 1) pin rst_in = 0 rst_in = 1 bms (pd_0) (pu_0) bm (pd) driven tmr0e (pd) driven buslock (pd_0) (pu_0) l1bcmpo (pu) driven tm2 (pu) driven tm3 (pu) driven pd = internal pull-down 5 k ; pu = internal pull-up 5 k ; pd_0 = internal pull-down 5 k on dsp id = 0; pu_0 = internal pull-up 5 k on dsp id = 0
rev. c | page 20 of 48 | december 2006 adsp-ts203s adsp-ts203sspecifications note that component specificatio ns are subject to change with out notice. for information on link port electrical characteris- tics, see link port low voltage, di fferential-signal (lvds) electrical characteristics, and timing on page 29 . operating conditions parameter description test conditions grade 1 1 specifications vary for different grades (for example, sabp-060, sabp-050, swbp-050). for more in formation on part grades, see ordering guide on page 45 . min typ max unit v dd internal supply voltage @ cclk = 500 mhz 050 1.00 1.05 1.10 v v dd_a analog supply voltage @ cclk = 500 mhz 050 1.00 1.05 1.10 v v dd_io i/o supply voltage (all) 2.38 2.50 2.63 v v dd_dram internal dram supply voltage @ cclk = 500 mhz 050 1.425 1.500 1.575 v t case case operating temperature a C40 +85 c v ih1 high level input voltage 2, 3 2 v ih1 specification applies to input and bidirectional pins: sclkrat2 C0, sclk, addr31C0, data63C0, rd , wrl , ack, brst , br7C0 , boff , hbr , hbg , mssd3C0 , ras , cas , sdcke, sdwe , tck, flag3C0, ds2C0, enedreg. 3 values represent dc case. during transitions, the inputs may overshoot or undershoot to the voltage shown in table 18 , based on the transient duty cycle. the dc case is equivalent to 100% duty cycle. @ v dd , v dd_io = max (all) 1.7 3.63 v v ih2 high level input voltage 3, 4 4 v ih2 specification applies to input and bidirectional pins: tdi, tms, trst, cimp1C0, id2C0, lxbcmpi , lxacki, por_in , rst_in , irq3C0 , cpa , dpa , dmar3C0 . @ v dd , v dd_io = max (all) 1.9 3.63 v v il low level input voltage 3, 5 5 applies to input an d bidirectional pins. @ v dd , v dd_io = min (all) C0.33 +0.8 v i dd v dd supply current, typical activity 6 6 for details on internal and external power calculation issues, including other oper ating conditions, see the ee-170, estimating power for the adsp-ts203s on the analog devices website. @ cclk = 500 mhz, v dd = 1.05 v, t case = 25c 050 2.06 a i dd_a v dd_a supply current, typical activity @ cclk = 500 mhz, v dd = 1.05 v, t case = 25c 050 20 50 ma i dd_io v dd_io supply current, typical activity 6 @ sclk = 62.5 mhz, v dd_io = 2.5 v, t case = 25c (all) 0.15 a i dd_dram v dd_dram supply current, typical activity 6 @ cclk = 500 mhz, v dd_dram = 1.5 v, t case = 25c 050 0.25 0.40 a v ref voltage reference (all) (v dd_io 0.56)5% v sclk_v ref voltage reference (all) (v clock _ drive 0.56) 5% v
adsp-ts203s rev. c | page 21 of 48 | december 2006 electrical characteristics table 18. maximum duty cycle for input transient voltage v in max (v) 1 v in min (v) 1 maximum duty cycle 2 +3.63 C0.33 100% +3.64 C0.34 90% +3.70 C0.40 50% +3.78 C0.48 30% +3.86 C0.56 17% +3.93 C0.63 10% 1 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. 2 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. this is equivalent to the measured durati on of a single instance of overshoot or undershoot as a percentage of the pe riod of occurrence. the practical worst case for peri od of occurrence for either overshoot or undershoot is 2 t sclk . parameter description test conditions min max unit v oh high level output voltage 1 1 applies to output an d bidirectional pins. @ v dd_io =min, i oh = C2 ma 2.18 v v ol low level output voltage 1 @ v dd_io =min, i ol =4 ma 0.4 v i ih high level input current @ v dd_io =max, v in =v ih max 20 a i ih_pu high level input current @ v dd_io =max, v in =v ih max 20 a i ih_pd high level input current @ v dd_io =max, v in =v dd_io max 0.3 0.76 ma i ih_pd_l high level input current @ v dd_io =max, v in =v ih max 3076a i il low level input current @ v dd_io =max, v in =0 v 20 a i il_pu low level input current @ v dd_io =max, v in =0 v 0.3 0.76 ma i il_pu_ad low level input current @ v dd_io =max, v in = 0 v 30 100 a i ozh three-state leakage current high @ v dd_io =max, v in =v ih max 50 a i ozh_pd three-state leakage current high @ v dd_io =max, v in =v dd_io max 0.3 0.76 ma i ozl three-state leakage current low @ v dd_io =max, v in =0 v 20 a i ozl_pu three-state leakage current low @ v dd_io =max, v in =0 v 0.3 0.76 ma i ozl_pu_ad three-state leakage current low @ v dd_io =max, v in = 0 v 30 100 a i ozl_od three-state leakage current low @ v dd_io =max, v in =0 v 4 7.6 ma c in input capacitance 2, 3 2 applies to all signals. 3 guaranteed but not tested. @ f in =1 mhz, t case = 25c, v in =2.5 v 3 pf parameter name suffix conventions: no suffix = appl ies to pins without pull-up or pull-down resistors, _pd = applies to pin types (pd) or (pd_0), _pu = applies to pin types (pu) or (pu_0), _pu_ad = applies to pin types (pu_ad), _od = applies to pin types od, _pd_l = applies to pin types (pd_l)
rev. c | page 22 of 48 | december 2006 adsp-ts203s package information the information presented in figure 8 provide details about the package branding for the adsp -ts203s processors. for a com- plete listing of prod uct availability, see ordering guide on page 45 . absolute maximum ratings stresses greater than those list ed below may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity figure 8. typical package brand table 19. package br and information brand key field description t temperature range pp package type z lead free option (optional) ccc see ordering guide lllllllll-l silicon lot number r.r silicon revision yyww date code vvvvvv assembly lot code lllllllll-l 2.0 tppz-ccc t adsp-ts20xs a yyww country_of_origin vvvvv table 20. absolute maximum ratings parameter rating internal (core) supply voltage (v dd )C0.3 v to +1.4 v analog (pll) supply voltage (v dd_a )C0.3 v to +1.4 v external (i/o) supply voltage (v dd_io )C0.3 v to +3.5 v external (dram) supply voltage (v dd_dram )C0.3 v to +2.1 v input voltage 1 1 applies to 10% transient duty cycle. for other duty cycles see table 18 . C0.63 v to +3.93 v output voltage swing C0.5 v to v dd_io +0.5 v storage temperature range C65c to +150c esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be take to avoid performance degradation or loss of functionality.
adsp-ts203s rev. c | page 23 of 48 | december 2006 timing specifications with the exception of dmar3C0 , irq3C0 , tmr0e, and flag3C0 (input only) pins, all ac timing for the adsp-ts203s processor is relative to a refe rence clock edge. because input setup/hold, output valid/hold, an d output enable/disable times are relative to a clock edge, the timing data for the adsp-ts203s processor has few calculated (formula-based) values. for information on ac timing, see general ac timing . for information on link port transfer timing, see link port low voltage, differential-signal (lvds) electrical characteristics, and timing on page 29 . general ac timing timing is measured on signals when they cross the 1.25 v level as described in figure 15 on page 28 . all delays (in nanosec- onds) are measured between the point that the first signal reaches 1.25 v and the point that the second signal reaches 1.25 v. the general ac timing data appears in table 22 and table 29 . all ac specifications are measured with the load specified in figure 36 on page 37 , and with the output drive strength set to strength 4. in order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to figure 37 on page 37 through figure 44 on page 38 (rise and fall time vs. load capacitance) and figure 45 on page 38 (out- put valid vs. load capacitance and drive strength). the ac asynchronous timing data for the irq3C0 , dmar3C0 , flag3C0, and tmr0e pins appears in table 21 . table 21. ac asynchronous signal specifications name description pulse width low (min) pulse width high (min) irq3C0 1 interrupt request 2 t sclk ns 2 t sclk ns dmar3C0 1 dma request 2 t sclk ns 2 t sclk ns flag3C0 2 flag3C0 input 2 t sclk ns 2 t sclk ns tmr0e 3 timer 0 expired 4 t sclk ns 1 these input pins have schmitt triggers and therefore do not need to be synchronized to a clock reference. 2 for output specifications on flag3C0 pins, see table 29 . 3 this pin is a strap option. during reset, an internal resistor pulls the pin low. table 22. reference clockscore clock (cclk) cycle time parameter description grade = 050 (500 mhz) unit min max t cclk 1 core clock cycle time 2.0 12.5 ns 1 cclk is the internal processor clock or instruction cycle time. th e period of this clock is equal to the system clock period (t sclk ) divided by the system clock ratio (sclkrat2C0). for information on avai lable part numbers for different in ternal processor clock rates, see the ordering guide on page 45 . figure 9. reference clockscore clock (cclk) cycle time cclk t cclk
rev. c | page 24 of 48 | december 2006 adsp-ts203s table 23. reference clockssystem clock (sclk) cycle time parameter description sclkrat = 4 , 6 , 8 , 10 , 12 sclkrat = 5 , 7 unit min max min max t sclk 1, 2, 3 system clock cycle time 8 50 8 50 ns t sclkh system clock cycle high time 0.40 t sclk 0.60 t sclk 0.45 t sclk 0.55 t sclk ns t sclkl system clock cycle low time 0.40 t sclk 0.60 t sclk 0.45 t sclk 0.55 t sclk ns t sclkf system clock transition timefalling edge 4 1.5 1.5 ns t sclkr system clock transition timerising edge 1.5 1.5 ns t sclkj 5, 6 system clock jitter tolerance 500 500 ps 1 for more information, see table 3 on page 12 . 2 for more information, see clock domains on page 9. 3 the value of (t sclk / sclkrat2-0) must not viol ate the specification for t cclk . 4 system clock transition times apply to minimum sclk cycle time (t sclk ) only. 5 actual input jitter should be combined with ac specifications for acc urate timing analysis. 6 jitter specification is maximum peak-to -peak time interval error (tie) jitter. figure 10. reference clockssystem clock (sclk) cycle time table 24. reference clocksjtag test clock (tck) cycle time parameter description min max unit t tck test clock (jtag) cycle time greater of 30 or t cclk 4ns t tckh test clock (jtag) cycle high time 12 ns t tckl test clock (jtag) cycle low time 12 ns figure 11. reference clocksjta g test clock (tck) cycle time sclk t sclk t sclkh t sclkl t sclkj t sclkf t sclkr tck t tck t tckh t tckl
adsp-ts203s rev. c | page 25 of 48 | december 2006 table 25. power-up timing 1 parameter min max unit timing requirement t vdd_dram v dd_dram stable after v dd , v dd_a , v dd_io stable >0 ms 1 for information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing . figure 12. power-up timing table 26. power-up reset timing parameter min max unit timing requirements t rst_in_pwr rst_in deasserted after v dd , v dd_a , v dd_io , v dd_dram , sclk, and static/ strap pins stable 2 ms t trst_in_pwr 1 trst asserted during power-up reset 100 t sclk ns switching characteristic t rst_out_pwr rst_out deasserted after rst_in deasserted 1.5 ms 1 applies after v dd , v dd_a , v dd_io , v dd_dram , and sclk are stable and before rst_in deasserted. figure 13. power -up reset timing v dd v dd_a v dd_io v dd_dram t vdd_dram rst_out rst_out_pwr trst trst_in_pwr sclk, dd, dd_a, dd_io, dd_dram staticstrap pins rst_in rst_in_pwr
rev. c | page 26 of 48 | december 2006 adsp-ts203s table 27. normal reset timing parameter min max unit timing requirements t rst_in rst_in asserted 2 ms t strap rst_in deasserted after strap pins stable 1.5 ms switching characteristic t rst_out rst_out deasserted after rst_in deasserted 1.5 ms figure 14. normal reset timing table 28. on-chip dram refresh 1 parameter min max unit timing requirement t ref on-chip dram refresh period 1.56 s 1 for more information on setting the refres h rate for the on-ch ip dram, refer to the adsp-ts201 tigersharc processor programming reference . strap pins t strap rst_in t rst_in rst_out t rst_out
adsp-ts203s rev. c | page 27 of 48 | december 2006 table 29. ac signal specifications (all values in this table are in nanoseconds.) name description input setup (min) input hold (min) output valid (max) output hold (min) output enable (min) 1 output disable (max) 1 reference clock addr31C0 external address bus 1.5 0.5 4.0 1.0 1.15 2.0 sclk data31C0 external data bus 1.5 0.5 4.0 1.0 1.15 2.0 sclk msh memory select host line 4.0 1.0 1.15 2.0 sclk mssd3C0 memory select sdram lines 1.5 0.5 4.0 1.0 1.0 2.0 sclk ms1C0 memory select for static blocks 4.0 1.0 1.15 2.0 sclk rd memory read 1.5 0.5 4.0 1.0 1.15 2.0 sclk wrl write low word 1.5 0.5 4.0 1.0 1.15 2.0 sclk ack acknowledge for data high to low 1.5 0.5 3.6 1.0 1.15 2.0 sclk acknowledge for data low to high 1.5 0.5 4.2 0.9 1.15 2.0 sclk sdcke sdram clock enable 1.5 0.5 4.0 1.0 1.15 2.0 sclk ras row address select 1.5 0.5 4.0 1.0 1.15 2.0 sclk cas column address select 1.5 0.5 4.0 1.0 1.15 2.0 sclk sdwe sdram write enable 1.5 0.5 4.0 1.0 1.15 2.0 sclk ldqm low word sdram data mask 4.0 1.0 1.15 2.0 sclk sda10 sdram addr10 4.0 1.0 1.15 2.0 sclk hbr host bus request 1.5 0.5 sclk hbg host bus grant 1.5 0.5 4.0 1.0 1.15 2.0 sclk boff back off request 1.50.5sclk buslock bus lock 4.0 1.0 1.15 2.0 sclk brst burst pin 1.5 0.5 4.0 1.0 1.15 2.0 sclk br7C0 multiprocessing bus request pins 1.5 0.5 4.0 1.0 sclk bm bus master debug aid only 4.0 1.0 sclk iord i/o read pin 4.0 1.0 1.0 2.0 sclk iowr i/o write pin 4.0 1.0 1.15 2.0 sclk ioen i/o enable pin 4.0 1.0 1.15 2.0 sclk cpa core priority access high to low 1.5 0.5 4.0 1.0 0.75 2.0 sclk core priority access low to high 1.5 0.5 29.5 2.0 0.75 2.0 sclk dpa dma priority access high to low 1.5 0.5 4.0 1.0 0.75 2.0 sclk dma priority access low to high 1.5 0.5 29.5 2.0 0.75 2.0 sclk bms boot memory select 4.0 1.0 1.15 2.0 sclk flag3C0 2 flag pins 4.0 1.0 1.15 2.0 sclk rst_in 3, 4 global reset pin 1.5 2.5 sclk 5 tms test mode select (jtag) 1.5 0.5 tck tdi test data input (jtag) 1.5 0.5 tck tdo test data output (jtag) 4.0 1.0 0.75 2.0 tck 6 trst 3, 4 test reset (jtag) 1.5 0.5 tck emu 7 emulation high to low 5.5 2.0 1.15 4.0 tck or sclk id2C0 8 static pinsmust be constant controlimp1C0 8 static pinsmust be constant ds2C0 8 static pinsmust be constant sclkrat2C0 8 static pinsmust be constant
rev. c | page 28 of 48 | december 2006 adsp-ts203s enedreg static pinsmust be connected to v ss strap sys 9, 10 strap pins 1.50.5sclk jtag sys 11, 12 jtag system pins +2.5 +10.0 +12.0 C1.0 tck 1 the external port protocols employ bus idle cycles for bus mastership transitions as well as slave address boundary crossings t o avoid any potential bus contention. the apparent driver overlap, due to output disables being larger than output enables, is not actual. 2 for input specifications on flag3C0 pins, see table 21 . 3 these input pins are asynchronous and therefore do no t need to be synchronized to a clock reference. 4 for additional requirement details, see reset and booting on page 9 . 5 rst_in clock reference is the falling edge of sclk. 6 tdo output clock reference is the falling edge of tck. 7 reference clock depends on function. 8 these pins may change only during re set; recommend connecting it to v dd_io /v ss . 9 strap pins include: bms , bm , buslock , tmr0e, l1bcmpo , tm2, and tm3. 10 specifications applicab le during reset only. 11 jtag system pins include: rst_in , rst_out , por_in , irq3C0 , dmar3C0 , hbr , boff , ms1C0 , msh , sdcke, ldqm, bms , iowr , iord , bm , emu , sda10, ioen , buslock , tmr0e, data31C0, addr31C0, rd , wrl , brst , mssd3C0 , ras , cas , sdwe , hbg , br7C0 , flag3C0, l0datop3C0, l0daton3C0, l1datop3C0, l1daton3C0, l0clkoutp, l0clkoutn, l1clkoutp, l1clkoutn, l0acki , l1acki, l0datip3C0, l0datin3C0, l1datip3C0, l1datin3C0, l0clkin p, l0clkinn, l1clkinp, l1clkinn, l0acko, l1acko, ack, cpa , dpa , l0bcmpo , l1bcmpo , l0bcmpi , l1bcmpi , id2C0, ctrl_impd1C0, sclkrat2C0, ds2C0, enedreg, tm2, tm3, tm4. 12 jtag system output timing clock refe rence is the falling edge of tck. figure 15. general ac parameters timing table 29. ac signal specifications (continued) (all values in this table are in nanoseconds.) name description input setup (min) input hold (min) output valid (max) output hold (min) output enable (min) 1 output disable (max) 1 reference clock reference clock input signal output signal three- state output valid output hold output enable output disable input hold input setup 1.25v 1.25v 1.25v t sclk or t tck
adsp-ts203s rev. c | page 29 of 48 | december 2006 link port low voltage, differential-signal (lvds) electrical characteristics, and timing table 30 and table 31 with figure 16 provide the electrical characteristics for the lvds link ports. the lvds link port sig- nal definitions represent all differential signals with a v od =0v level and use signal naming without n (negative) and p (posi- tive) suffixes (see figure 17 ). table 30. link port lvds transm it electrical characteristics parameter description test conditions min max unit v oh output voltage high, v o_p or v o_n r l = 100 1.85 v v ol output voltage low, v o_p or v o_n r l = 100 0.92 v |v od | output differential voltage r l = 100 300 650 mv i os short-circuit output current v o_p or v o_n = 0 v +5/C55 ma v od = 0 v 10 ma v ocm common-mode output voltage 1.20 1.50 v table 31. link port lvds receive electrical characteristics parameter description test conditions min max unit |v id | differential input voltage t ldis /t ldih 0.20 ns t ldis /t ldih 0.25 ns t ldis /t ldih 0.30 ns t ldis /t ldih 0.35 ns 250 217 206 195 850 850 850 850 mv mv mv mv v icm common-mode input voltage 0.6 1.57 v figure 16. link portstransmit electrical characteristics figure 17. link portssignals definition v o_n v o_p r l v ocm = (v o_p +v o_n ) 2 v od =(v o_p ?v o_n ) lxn lxp lx di fferen ti al pa ir wave forms di fferen tial voltage waveform v od =0v v o_n v o_p v od =v o_p ?v o_n
rev. c | page 30 of 48 | december 2006 adsp-ts203s link portdata out timing table 32 with figure 18 , figure 19 , figure 20 , figure 21 , figure 22 , and figure 23 provide the data out timing for the lvds link ports. table 32. link portdata out timing parameter description min max unit outputs t reo rising edge ( figure 19 )350ps t feo falling edge ( figure 19 )350ps t lclkop lxclkout period ( figure 18 ) greater of 4.0 or 0.9 lcr t cclk 1, 2, 3 smaller of 12.5 or 1.1 lcr t cclk 1, 2, 3 ns t lclkoh lxclkout high ( figure 18 )0.4 t lclkop 1 0.6 t lclkop 1 ns t lclkol lxclkout low ( figure 18 )0.4 t lclkop 1 0.6 t lclkop 1 ns t cojt lxclkout jitter ( figure 18 ) 150 4, 5, 6 250 7 ps ps t ldos lxdato output setup ( figure 20 )0.25 lcr t cclk C0.10 t cclk 1, 4, 8 0.25 lcr t cclk C0.15 t cclk 1, 5, 6, 8 0.25 lcr t cclk C0.30 t cclk 1, 7, 8 ns ns ns t ldoh lxdato output hold ( figure 20 )0.25 lcr t cclk C0.10 t cclk 1, 4, 8 0.25 lcr t cclk C0.15 t cclk 1, 5, 6, 8 0.25 lcr t cclk C0.30 t cclk 1, 7, 8 ns ns ns t lackid delay from lxacki rising edge to first trans- mission clock edge ( figure 21 ) 16 lcr t cclk 1, 2 ns t bcmpov lxbcmpo valid ( figure 21 )2 lcr t cclk 1, 2 ns t bcmpoh lxbcmpo hold ( figure 22 )3 tsw C 0.5 1, 9 ns inputs t lackis lxacki low setup to guarantee that the trans- mitter stops transmitting ( figure 22 ) lxacki high setup to guarantee that the trans- mitter continues its transmission without any interruption ( figure 23 )16 lcr t cclk 1, 2 ns t lackih lxacki high hold time ( figure 23 )0.51 ns 1 timing is relative to the 0 differential voltage (v od = 0). 2 lcr (link port clock ratio) = 1, 1.5, 2, or 4. t cclk is the core period. 3 for the cases of t lclkop = 4.0 ns and t lclkop = 12.5 ns, the effect of t cojt specification on output period must be considered. 4 lcr= 1. 5 lcr= 1.5. 6 lcr= 2. 7 lcr= 4. 8 the t ldos and t ldoh values include lclkout jitter. 9 tsw is a short-word transmission period. for a 4-bit link, it is 2 lcr t cclk . for a 1-bit link, it is 8 lcr t cclk ns.
adsp-ts203s rev. c | page 31 of 48 | december 2006 figure 18. link portsoutput clock figure 19. link portsdifferential output signals transition time lxclkout v od =0v t cojt t lclkol t lclkoh t lclkop + | v od | min - | v od | min v od =0v t reo t feo v o_n v o_p r l c l c l_p c l_n r l =100 c l =0.1pf c l_p =5pf c l_n =5pf figure 20. link portsdata output setup and hold 1 1 these parameters are valid for both clock edges. lxclkout lxdato v od =0v v od =0v t ldos t ldoh t ldos t ldoh figure 21. link portstransmission start lxclkout lxdato v od =0v v od =0v t lackid t bcmpov lxacki lxbcmpo
rev. c | page 32 of 48 | december 2006 adsp-ts203s figure 22. link portstransmission end and stops figure 23. link portsback to back transmission lxclkout lxdato v od =0v v od =0v first edge of 5th short word in a quad word t lackis t bcmpoh lxacki lxbcmpo t lackih last edge in a quad word lxclkout lxdato v od =0v v od =0v t lackis lxacki t lackih last edge in a quad word
adsp-ts203s rev. c | page 33 of 48 | december 2006 link portdata in timing table 33 with figure 24 and figure 25 provide the data in timing for the lvds link ports. table 33. link portdata in timing parameter description min max unit inputs t lclkip lxclkin period ( figure 25 ) greater of 1.8 or 0.9 t cclk 1 12.5 ns t ldis lxdati input setup ( figure 25 )0.20 1, 2 0.25 1, 3 0.30 1, 4 0.35 1, 5 ns ns ns ns t ldih lxdati input hold ( figure 25 )0.20 1, 2 0.25 1, 3 0.30 1, 4 0.35 1, 5 ns ns ns ns t bcmpis lxbcmpi setup ( figure 24 )2t lclkip 1 ns t bcmpih lxbcmpi hold ( figure 24 )2t lclkip 1 ns 1 timing is relative to the 0 differential voltage (v od = 0). 2 |v id | = 250 mv 3 |v id | = 217 mv 4 |v id | = 206 mv 5 |v id | = 195 mv figure 24. link portslast received quad word lxclkin lxdati v od =0v v od =0v t bcmpis lxbcmpi t bcmpih first edge in fifth short word in a quad word
rev. c | page 34 of 48 | december 2006 adsp-ts203s figure 25. link portsda ta input setup and hold 1 1 these parameters are valid for both clock edges. lxclkin lxdati v od =0v v od =0v t ldis t ldih t ldis t ldih t lclkip
adsp-ts203s rev. c | page 35 of 48 | december 2006 output drive currents figure 26 through figure 33 show typical iCv characteristics for the output drivers of the adsp-t s203s processor. the curves in these diagrams represent the current drive capability of the out- put drivers as a function of output voltage over the range of drive strengths. for complete outp ut driver characteristics, refer to the dsps ibis models, availa ble on the analog devices web- site ( www.analog.com ). figure 26. typical drive currents at strength 0 figure 27. typical drive currents at strength 1 output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) ?2.5 0 2.5 v dd_io = 2.38v, +105c ?5.0 ?7.5 ?10.0 ?12.5 ?15.0 5.0 7.5 10.0 12.5 15.0 strength 0 v dd_io =2.5v,+25c v dd_io = 2.63v, ?40c i ol i oh v dd_io =2.38v,+105c v dd_io =2.5v,+25c v dd_io =2.63v,?40c output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) ?5 0 5 v dd_io = 2.38v, +105c ?10 ?15 ?20 ?25 10 15 20 25 30 strength 1 v dd_io =2.5v,+25c v dd_io = 2.63v, ?40c i ol i oh v dd_io = 2.38v, +105c v dd_io =2.5v,+25c v dd_io = 2.63v, ?40c ?30 figure 28. typical driv e currents at strength 2 figure 29. typical driv e currents at strength 3 figure 30. typical driv e currents at strength 4 output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) ?9 0 9 v dd_io = 2.38v, +105c ?18 ?27 ?36 ?45 18 36 45 strength 2 v dd_io = 2.5v, +25c v dd_io = 2.63v, ?40c i ol i oh v dd_io = 2.38v, +105c v dd_io = 2.5v, +25c v dd_io = 2.63v, ?40c 27 output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) ?11 0 11 v dd_io = 2.38v, +105c ?22 ?33 ?44 ?55 22 33 44 55 strength 3 v dd_io =2.5v,+25c v dd_io = 2.63v, ?40c i ol i oh v dd_io = 2.38v, +105c v dd_io =2.5v,+25c v dd_io = 2.63v, ?40c output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) ?10 0 10 v dd_io = 2.38v, +105c ?20 ?30 ?40 ?60 20 30 40 60 70 strength 4 v dd_io =2.5v,+25c v dd_io = 2.63v, ?40c i ol i oh v dd_io = 2.38v, +105c v dd_io =2.5v,+25c v dd_io =2.63v,?40c 50 ?50 ?70
rev. c | page 36 of 48 | december 2006 adsp-ts203s test conditions the ac signal specifications (timing parameters) appear in table 29 on page 27 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the dsp apply for the voltage reference levels in figure 34 . output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the fol- lowing equation: the output disable time t dis is the difference between t measured_dis and t decay as shown in figure 35 . the time t measured_dis is the interval from when the reference signal switches to when the output voltage decays v from the mea- sured output high or output low voltage. t decay is calculated with test loads c l and i l , and with v equal to 0.4 v. figure 31. typical drive currents at strength 5 figure 32. typical drive currents at strength 6 figure 33. typical drive currents at strength 7 output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) 11 0 11 v dd_io = 2.38v, 105c 22 33 44 66 22 33 44 66 88 strength 5 v dd_io =2.5v,25c v dd_io = 2.63v, 40c i ol i oh v dd_io = 2.38v, 105c v dd_io =2.5v,25c v dd_io = 2.63v, 40c 77 55 55 88 77 output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) 0 10 20 v dd_io = 2.38v, 105c 10 20 30 40 100 30 40 50 60 100 strength 6 v dd_io =2.5v,25c v dd_io = 2.63v, 40c i ol i oh v dd_io =2.38v,105c v dd_io =2.5v,25c v dd_io = 2.63v, 40c 70 80 90 50 60 70 80 90 output pin voltage (v) 02.8 0.4 0.8 1.2 1.6 2.0 2.4 o u t p u t p i n c u r r e n t ( m a ) 10 0 10 v dd_io = 2.38v, 105c 20 30 40 50 110 20 30 40 50 110 strength 7 v dd_io =2.5v,25c v dd_io = 2.63v, 40c i ol i oh v dd_io = 2.38v, 105c v dd_io =2.5v,25c v dd_io =2.63v,40c 60 70 80 90 100 60 70 80 90 100 figure 34. voltage reference levels for ac measurements (except output enable/disable) figure 35. output enable/disable input or output 1.25v 1.25v t decay c l v () i l ? = reference signal t dis output starts driving v oh (measured) ? v v ol (measured) + v t measured_dis v oh (measured) v ol (measured) 1.65v 0.85v high impedance state. test conditions cause this voltage to be approximately 1.25v. output stops driving t decay t ena t measured_ena t ramp
adsp-ts203s rev. c | page 37 of 48 | december 2006 output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. the time for the voltag e on the bus to ramp by v is dependent on the capacitive load, c l , and the drive current, i d . this ramp time can be approxima ted by the following equation: the output enable time t ena is the difference between t measured_ena and t ramp as shown in figure 35 . the time t measured_ena is the interval from wh en the reference signal switches to when the output voltage ramps v from the mea- sured three-stated output level. t ramp is calculated with test load c l , drive current i d , and with v equal to 0.4 v. capacitive loading output valid and hold are based on standard capacitive loads: 30 pf on all pins (see figure 36 ). the delay and hold specifica- tions given should be derated by a drive strength related factor for loads other than the nominal value of 30 pf. figure 37 through figure 44 show how output rise time varies with capac- itance. figure 45 graphically shows how ou tput valid varies with load capacitance. (note that this graph or derating does not apply to output disable delays; see output disable time on page 36 .) the graphs of figure 37 through figure 45 may not be linear outside the ranges shown. figure 36. equivalent device loading for ac measurements (includes all fixtures) figure 37. typical outp ut rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 0 t ramp c l v () i d ? = 1.25v to output pin 30pf 50 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 rise time y = 0.259x + 3.0842 strength 0 (v dd_io =2.5v) r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) fall time y = 0.251x + 4.2245 figure 38. typical output rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 1 figure 39. typical output rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 2 figure 40. typical output rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 3 0 102030 405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) strength 1 (v dd_io =2.5v) rise time = 0.1501 x 0.05 fall time = 0.1527x 0.7485 0 102030405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) strength 2 (v dd_io =2.5v) rise time = 0.0861 x 0.4712 fall time = 0.0949x 0.8112 0 102030405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) strength 3 (v dd_io =2.5v) rise time =0.06 x 1.1362 fall time = 0.0691x 1.1158
rev. c | page 38 of 48 | december 2006 adsp-ts203s figure 41. typical outp ut rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 4 figure 42. typical outp ut rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 5 figure 43. typical outp ut rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 6 r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 strength 4 (v dd_io =2.5v ) rise time y = 0.0573x + 0.9789 fall time y = 0.0592x + 1.0629 r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 rise time y = 0.0481 x +0.7889 fall time y = 0.0493x + 0.8389 strength 5 (v dd_io =2.5v) r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 rise time y = 0.0377 x +0.7449 fall time y = 0.0374x + 0.851 strength 6 (v dd_io =2.5v) figure 44. typical output rise and fall time (10% to 90%, v dd_io =2.5v) vs. load capacitance at strength 7 figure 45. typical output valid (v dd_io = 2.5 v) vs. load capacitance at max case temperature and strength 0 to 7 1 1 the line equations for the output valid vs. load capacitance are: strength 0: y = 0.0956x + 3.5662 strength 1: y = 0.0523x + 3.2144 strength 2: y = 0.0433x + 3.1319 strength 3: y = 0.0391x + 2.9675 strength 4: y = 0.0393x + 2.7653 strength 5: y = 0.0373x + 2.6515 strength 6: y = 0.0379x + 2.1206 strength 7: y = 0.0399x + 1.9080 r i s e a n d f a l l t i m e s ( n s ) load capacitance (pf) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 strength 7 (v dd_io =2.5v) rise time y = 0.0321 x +0.6512 fall time y = 0.0313x + 0.818 0 102030405060708090100 0 5 10 15 o u t p u t v a l i d ( n s ) load capacitance (pf) 1 2 3 4 5 6 7 strength 0?7 (v dd_io =2.5v) 0
adsp-ts203s rev. c | page 39 of 48 | december 2006 environmental conditions the adsp-ts203s processor is rated for performance under t case environmental conditions specified in the operating con- ditions on page 20 . thermal characteristics the adsp-ts203s processor is packaged in a 25 mm 25 mm, thermally enhanced ball gr id array (bga_ed). the adsp-ts203s processor is spec ified for a case temperature (t case ). to ensure that the t case data sheet specification is not exceeded, a heat sink and/or an air flow source may be required. table 34 shows the thermal ch aracteristics of the 25 mm 25 mm bga_ed package. all parameters are based on a jesd51-9 four-layer 2s2p boar d. all data are based on 3 w power dissipation. table 34. thermal characteristics for 25 mm 25 mm package parameter condition typical unit ja 1 1 ja measured per jedec standard jesd51-6. airflow = 0 m/s 12.9 2 2 ja = 12.9c/w for 0 m/s is for vertical ly mounted boards. for horizontally mounted boards, use 17.0c/w for 0 m/s. c/w airflow = 1 m/s 10.2 c/w airflow = 2 m/s 9.0 c/w airflow = 3 m/s 8.0 c/w jb 3 3 jb measured per jedec standard jesd51-9. 7.7c/w jc 4 4 jc measured by cold plate test method (no approved jedec standard). 0.7c/w
rev. c | page 40 of 48 | december 2006 adsp-ts203s 576-ball bga_ed pin configurations figure 46 shows a summary of pin configurations for the 576-ball bga_ed package, and table 35 lists the signal-to-ball assignments. figure 46. 576-ball bga_ed pin configurations 1 (top view, summary) 1 for a more detailed pin summary diagram, see the ee-179: adsp-ts201s system design guidelines on the analog devices website ( www.analog.com ). top view 19 17 21 23 15 13 11 9 57 3 1 20 18 16 14 12 10 8 6 24 22 24 r p n m l k j h g f e d c b a y w v u t ad ac ab aa v dd v dd_io v dd_dram v ss signal v dd_a v ref key: no connect
adsp-ts203s rev. c | page 41 of 48 | december 2006 table 35. 576-ball (25 mm 25 mm) bga_ed ball assignments ball no. signal name ball no. signal name ball no. signal name ball no. signal name a1 v ss b1 nc c1 v ss d1 nc a2 nc b2 v ss c2 v ss d2 nc a3 v ss b3 v ss c3 v ss d3 nc a4 nc b4 nc c4 nc d4 v ss a5 nc b5 nc c5 nc d5 nc a6 nc b6 nc c6 nc d6 nc a7 nc b7 nc c7 nc d7 nc a8 nc b8 nc c8 nc d8 nc a9 data29 b9 data30 c9 data31 d9 nc a10 data25 b10 data26 c10 data27 d10 data28 a11 data23 b11 data24 c11 data21 d11 data22 a12 data19 b12 data20 c12 data17 d12 data18 a13 data15 b13 data16 c13 v ss d13 v ss a14 data11 b14 data12 c14 data13 d14 data14 a15 data9 b15 data10 c15 data7 d15 data8 a16 data5 b16 data6 c16 data3 d16 data4 a17 data1 b17 data2 c17 ack d17 data0 a18 wrl b18 tm4 c18 rd d18 brst a19 addr30 b19 addr31 c19 addr26 d19 addr27 a20 addr28 b20 addr29 c20 addr24 d20 addr25 a21 addr22 b21 addr23 c21 addr20 d21 v ss a22 v ss b22 v ss c22 v ss d22 addr19 a23 addr21 b23 v ss c23 v dd_io d23 addr17 a24 v ss b24 addr18 c24 v dd_io d24 addr16 e1 nc f1 nc g1 mssd1 h1 v ss e2 nc f2 ms1 g2 v ss h2 msh e3 nc f3 nc g3 ms0 h3 mssd3 e4 nc f4 nc g4 bms h4 sclkrat0 e5 v ss f5 v dd_io g5 v ss h5 v dd_io e6 v dd_io f6 v dd g6 v dd h6 v dd e7 v ss f7 v dd g7 v dd h7 v dd e8 v dd_io f8 v dd g8 v dd h8 v ss e9 v ss f9 v dd g9 v dd h9 v ss e10 v dd_io f10 v dd g10 v dd h10 v ss e11 v dd_io f11 v dd_dram g11 v dd_dram h11 v ss e12 v dd_io f12 v dd_dram g12 v dd_dram h12 v ss e13 v dd_io f13 v dd g13 v dd h13 v ss e14 v dd_io f14 v dd g14 v dd h14 v ss e15 v dd_io f15 v dd_dram g15 v dd_dram h15 v ss e16 v ss f16 v dd_dram g16 v dd_dram h16 v ss e17 v dd_io f17 v dd g17 v dd h17 v ss e18 v ss f18 v dd g18 v dd h18 v dd e19 v dd_io f19 v dd g19 v dd h19 v dd e20 v ss f20 v dd_io g20 v dd_io h20 v dd_io e21 addr15 f21 addr13 g21 addr7 h21 addr3 e22 addr14 f22 addr12 g22 addr6 h22 addr2 e23 addr11 f23 addr9 g23 addr5 h23 addr1 e24 addr10 f24 addr8 g24 addr4 h24 addr0
rev. c | page 42 of 48 | december 2006 adsp-ts203s j1 ras k1 sda10 l1 sdwe m1 br3 j2 cas k2 sdcke l2 br0 m2 sclkrat1 j3 v ss k3 ldqm l3 br1 m3 br5 j4 v ref k4 nc l4 br2 m4 br6 j5 v ss k5 v dd_io l5 v dd_io m5 v dd_io j6 v dd k6 v dd l6 v dd m6 v dd j7 v dd k7 v dd l7 v dd m7 v dd j8 v ss k8 v ss l8 v ss m8 v ss j9 v ss k9 v ss l9 v ss m9 v ss j10 v ss k10 v ss l10 v ss m10 v ss j11 v ss k11 v ss l11 v ss m11 v ss j12 v ss k12 v ss l12 v ss m12 v ss j13 v ss k13 v ss l13 v ss m13 v ss j14 v ss k14 v ss l14 v ss m14 v ss j15 v ss k15 v ss l15 v ss m15 v ss j16 v ss k16 v ss l16 v ss m16 v ss j17 v ss k17 v ss l17 v ss m17 v ss j18 v dd k18 v dd_dram l18 v dd_dram m18 v dd j19 v dd k19 v dd_dram l19 v dd_dram m19 v dd j20 v ss k20 v dd_io l20 v dd_io m20 v dd_io j21 l0acko k21 l0dati1_n l21 l0dati3_n m21 v ss j22 l0bcmpi k22 l0dati1_p l22 l0dati3_p m22 v ss j23 l0dati0_n k23 l0clkinn l23 l0dati2_n m23 l0dato3_n j24 l0dati0_p k24 l0clkinp l24 l0dati2_p m24 l0dato3_p n1 id0 p1 sclk r1 v ss t1 rst_in n2 v ss p2 sclk_vref r2 nc (sclk) 1 t2 sclkrat2 n3 v dd_a p3 v ss r3 nc (sclk_vref) 1 t3 br4 n4 v dd_a p4 bm r4 br7 t4 ds0 n5 v dd_io p5 v dd_io r5 v dd_io t5 v ss n6 v dd p6 v dd r6 v dd t6 v dd n7 v dd p7 v dd r7 v dd t7 v dd n8 v ss p8 v ss r8 v ss t8 v ss n9 v ss p9 v ss r9 v ss t9 v ss n10 v ss p10 v ss r10 v ss t10 v ss n11 v ss p11 v ss r11 v ss t11 v ss n12 v ss p12 v ss r12 v ss t12 v ss n13 v ss p13 v ss r13 v ss t13 v ss n14 v ss p14 v ss r14 v ss t14 v ss n15 v ss p15 v ss r15 v ss t15 v ss n16 v ss p16 v ss r16 v ss t16 v ss n17 v ss p17 v ss r17 v ss t17 v ss n18 v dd p18 v dd_dram r18 v dd_dram t18 v dd n19 v dd p19 v dd_dram r19 v dd_dram t19 v dd n20 v dd_io p20 v dd_io r20 v dd_io t20 v ss n21 l0dato2_n p21 l0dato1_n r21 nc t21 l1dati0_n n22 l0dato2_p p22 l0dato1_p r22 v ss t22 l1dati0_p n23 l0clkon p23 l0dato0_n r23 l0bcmpo t23 l1acko n24 l0clkop p24 l0dato0_p r24 l0acki t24 l1bcmpi table 35. 576-ball (25 mm 25 mm) bga_ ed ball assignments (continued) ball no. signal name ball no. signal name ball no. signal name ball no. signal name
adsp-ts203s rev. c | page 43 of 48 | december 2006 u1 mssd0 v1 mssd2 w1 controlimp0 y1 emu u2 rst_out v2 ds2 w2 enedreg y2 tck u3 id2 v3 por_in w3 tdi y3 tmr0e u4 ds1 v4 controlimp1 w4 tdo y4 flag3 u5 v dd_io v5 v ss w5 v dd_io y5 v ss u6 v dd v6 v dd w6 v dd y6 v dd_io u7 v dd v7 v dd w7 v dd y7 v ss u8 v ss v8 v dd w8 v dd y8 v dd_io u9 v ss v9 v dd w9 v dd y9 v ss u10 v dd v10 v dd w10 v dd y10 v dd_io u11 v dd_dram v11 v dd_dram w11 v dd_dram y11 v dd_io u12 v ss v12 v dd_dram w12 v dd_dram y12 v dd_io u13 v ss v13 v dd w13 v dd y13 v dd_io u14 v ss v14 v dd w14 v dd y14 v dd_io u15 v ss v15 v dd_dram w15 v dd_dram y15 v dd_io u16 v ss v16 v dd_dram w16 v dd_dram y16 v ss u17 v ss v17 v dd w17 v dd y17 v dd_io u18 v dd v18 v dd w18 v dd y18 v ss u19 v dd v19 v dd w19 v dd y19 v dd_io u20 v dd_io v20 v dd_io w20 v dd_io y20 v ss u21 l1clkinn v21 l1dati3_n w21 l1clkon y21 l1dato1_n u22 l1clkinp v22 l1dati3_p w22 l1clkop y22 l1dato1_p u23 l1dati1_n v23 l1dati2_n w23 l1dato3_n y23 l1dato2_n u24 l1dati1_p v24 l1dati2_p w24 l1dato3_p y24 l1dato2_p aa1 flag2 ab1 v ss ac1 flag0 ad1 v ss aa2 flag1 ab2 v ss ac2 v ss ad2 id1 aa3 irq3 ab3 v ss ac3 v dd_io ad3 v dd_io aa4 v ss ab4 nc ac4 tms ad4 trst aa5 irq0 ab5 irq2 ac5 iowr ad5 iord aa6 ioen ab6 irq1 ac6 dmar2 ad6 dmar3 aa7 dmar0 ab7 dmar1 ac7 cpa ad7 dpa aa8 hbr ab8 hbg ac8 boff ad8 buslock aa9 tm3 ab9 v dd_io ac9 nc ad9 nc aa10 nc ab10 nc ac10 nc ad10 nc aa11 nc ab11 nc ac11 nc ad11 nc aa12 v ss ab12 v ss ac12 v dd_io ad12 v dd_io aa13 v dd_io ab13 v dd_io ac13 v ss ad13 v dd_io aa14 v dd_io ab14 v dd_io ac14 v dd_io ad14 v dd_io aa15 nc ab15 v ss ac15 nc ad15 v ss aa16 nc ab16 nc ac16 tm2 ad16 v dd_io aa17 nc ab17 nc ac17 nc ad17 nc aa18 nc ab18 nc ac18 nc ad18 nc aa19 v ss ab19 v dd_io ac19 v dd_io ad19 v dd_io aa20 v dd_io ab20 v dd_io ac20 v dd_io ad20 v dd_io aa21 v ss ab21 nc ac21 v dd_io ad21 v dd_io aa22 l1bcmpo ab22 v ss ac22 v dd_io ad22 v dd_io aa23 l1dato0_n ab23 v dd_io ac23 v ss ad23 v ss aa24 l1dato0_p ab24 v dd_io ac24 l1acki ad24 v ss 1 on revision 1.x silicon, the r2 and r3 balls are nc. on revision 0.x silicon, the r2 ball is sclk, and the r3 ball is sclk_v ref . for more information on sclk and sclk_v ref on revision 0.x silicon, see the ee-179: adsp-ts20x tigersharc system desi gn guidelines on the analog devices website ( www.analog.com ). table 35. 576-ball (25 mm 25 mm) bga_ ed ball assignments (continued) ball no. signal name ball no. signal name ball no. signal name ball no. signal name
rev. c | page 44 of 48 | december 2006 adsp-ts203s outline dimensions the adsp-ts203s processor is available in a 25 mm 25 mm, 576-ball metric therma lly enhanced ball grid array (bga_ed) package with 24 rows of balls (bp-576). surface mount design the following table is provided as an aide to pcb design. the numbers listed in the table ar e for reference purposes and should not supersede the pcb de sign rules. please reference ipc-7351, surface mount design and land pattern standard , for pcb design recommendations. figure 47. 576-ball bga_ed (bp-576) 1.00 bsc (ball pitch) 0.75 0.65 0.55 (ball diameter) detail a notes: 1. all dimensions are in millimeters. 2. the actual position of the ball grid is within 0.25 mm of its ideal position relative to the package edges. 3. center dimensions are nominal. 4. this package conforms to jedec ms-034 specification. seating plane 1.60 max 0.20 max detail a 0.97 bsc 7 9531 11 13 15 17 21 19 23 6 8 10 12 14 16 18 20 24 22 42 r p n m l k j h g f e d c b a y w v u t ad ac ab aa 23.00 bsc sq 25.20 25.00 24.80 25.20 25.00 24.80 top view bottom view 1.00 bsc 0.60 0.50 0.40 1.00 bsc a1 ball indicator 1.25 1.00 0.75 1.25 1.00 0.75 3.10 2.94 2.78 package ball attach type solder mask opening ball pad size 576-ball bga_ed (bp-576-1) nonsolder mask defined (nsmd) 0.69 0.56
adsp-ts203s rev. c | page 45 of 48 | december 2006 ordering guide model temperature range 1 1 represents case temperature. instruction rate 2 2 the instruction rate is the same as the internal processor core clock (cclk) rate. on-chip dram operating voltage package option package description ADSP-TS203SABP-050 C40c to +85c 500 mhz 4m bit 1.05 v dd , 2.5 v dd_io , 1.5 v dd_dram bp-576 576-ball bga_ed adsp-ts203sabpz050 3 3 z = pb-free part. C40c to +85c 500 mhz 4m bit 1.05 v dd , 2.5 v dd_io , 1.5 v dd_dram bp-576 576-ball bga_ed
rev. c | page 46 of 48 | december 2006 adsp-ts203s
adsp-ts203s rev. c | page 47 of 48 | december 2006
rev. c | page 48 of 48 | december 2006 adsp-ts203s ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c04 326-0-12/06(c)

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